Universal Electronics Accessoires pour consoles de jeux téléchargement des manuels d'utilisation À partir de m

Modèles	Type de document
Mary Battery	Manuel d'utilisateur Universal Electronics Mary Battery User's Manual, 1 pages

PERIPHERALS

1

DIGITAL I/O

1

2 Rev. 1.4

2

Table of Contents

3

4 Rev. 1.3

4

Rev. 1.3 5

5

6 Rev. 1.3

6

Rev. 1.3 7

7

List of Figures

8

Rev. 1.3 9

9

10 Rev. 1.3

10

List of Tables

11

12 Rev. 1.3

12

List of Registers

13

14 Rev. 1.3

14

Rev. 1.3 15

15

16 Rev. 1.3

16

1. System Overview

17

Rev. 1.3 19

19

20 Rev. 1.3

20

Rev. 1.3 21

21

200 ksps

23

2. Absolute Maximum Ratings

24

Rev. 1.3 25

25

Rev. 1.3 27

27

28 Rev. 1.3

28

Rev. 1.3 29

29

30 Rev. 1.3

30

C8051F340/1/4/5/8/C-GQ

31

Top View

31

C8051F342/3/6/7/9/A/B/D-GQ

34

C8051F342/3/6/7/9/A/B-GM

37

C1 4.80 4.90 X2 3.20 3.40

40

C2 4.80 4.90 Y1 0.75 0.85

40

E 0.50 BSC Y2 3.20 3.40

40

X1 0.20 0.30

40

Rev. 1.3 41

41

5.1. Analog Multiplexer

42

5.2. Temperature Sensor

43

Temperature (degrees C)

44

5.3. Modes of Operation

45

5.3.2. Tracking Modes

46

Differential Mode

47

Single-Ended Mode

47

48 Rev. 1.3

48

Rev. 1.3 49

49

50 Rev. 1.3

50

(bit addressable)

51

52 Rev. 1.3

52

Rev. 1.3 53

53

54 Rev. 1.3

54

Rev. 1.3 55

55

–15 0 +15 LSB

56

Rev. 1.3 57

57

58 Rev. 1.3

58

7. Comparators

59

60 Rev. 1.3

60

Rev. 1.3 61

61

62 Rev. 1.3

62

Rev. 1.3 63

63

64 Rev. 1.3

64

Rev. 1.3 65

65

66 Rev. 1.3

66

Rev. 1.3 67

67

68 Rev. 1.3

68

8. Voltage Regulator (REG0)

69

70 Rev. 1.3

70

Rev. 1.3 71

71

72 Rev. 1.3

72

9. CIP-51 Microcontroller

73

9.1. Instruction Set

74

Rev. 1.3 75

75

76 Rev. 1.3

76

Rev. 1.3 77

77

78 Rev. 1.3

78

9.2. Memory Organization

79

9.2.1. Program Memory

80

9.2.2. Data Memory

81

9.2.5. Stack

81

82 Rev. 1.3

82

Rev. 1.3 83

83

84 Rev. 1.3

84

Rev. 1.3 85

85

9.2.7. Register Descriptions

86

Rev. 1.3 87

87

9.3. Interrupt Handler

88

9.3.3. Interrupt Priorities

89

9.3.4. Interrupt Latency

89

90 Rev. 1.3

90

Rev. 1.3 91

91

92 Rev. 1.3

92

Rev. 1.3 93

93

94 Rev. 1.3

94

Rev. 1.3 95

95

96 Rev. 1.3

96

9.4. Power Management Modes

97

98 Rev. 1.3

98

10. Prefetch Engine

99

11. Reset Sources

100

11.1. Power-On Reset

101

Figure 11.2. Power-On and V

101

Monitor Reset Timing

101

Monitor Control

102

11.2. Power-Fail Reset / V

102

Monitor

102

11.3. External Reset

103

11.5. Comparator0 Reset

103

11.7. Flash Error Reset

103

11.8. Software Reset

104

11.9. USB Reset

104

Rev. 1.3 105

105

106 Rev. 1.3

106

12. Flash Memory

107

12.1.3. Flash Write Procedure

108

12.3. Security Options

109

110 Rev. 1.3

110

Rev. 1.3 111

111

112 Rev. 1.3

112

Rev. 1.3 113

113

13.1. Accessing XRAM

114

USB FIFO Space

115

13.4. Port Configuration

116

Rev. 1.3 117

117

118 Rev. 1.3

118

(Optional)

119

13.6.1. Internal XRAM Only

121

13.7. Timing

122

Rev. 1.3 123

123

13.7.1. Non-multiplexed Mode

124

Rev. 1.3 125

125

126 Rev. 1.3

126

13.7.2. Multiplexed Mode

127

128 Rev. 1.3

128

Rev. 1.3 129

129

130 Rev. 1.3

130

*Note: T

130

14. Oscillators

131

132 Rev. 1.3

132

Rev. 1.3 133

133

134 Rev. 1.3

134

Rev. 1.3 135

135

14.3.3. External RC Example

136

Rev. 1.3 137

137

14.4. 4x Clock Multiplier

138

14.5.2. USB Clock Selection

139

140 Rev. 1.3

140

Rev. 1.3 141

141

15. Port Input/Output

142

Rev. 1.3 143

143

144 Rev. 1.3

144

(No Pins Skipped)

145

146 Rev. 1.3

146

15.2. Port I/O Initialization

147

148 Rev. 1.3

148

Rev. 1.3 149

149

150 Rev. 1.3

150

Rev. 1.3 151

151

152 Rev. 1.3

152

Rev. 1.3 153

153

154 Rev. 1.3

154

Rev. 1.3 155

155

156 Rev. 1.3

156

Rev. 1.3 157

157

158 Rev. 1.3

158

Rev. 1.3 159

159

16.1. Endpoint Addressing

160

16.2. USB Transceiver

160

PHYTST[1:0] Mode D+ D–

161

16.3. USB Register Access

162

Rev. 1.3 163

163

164 Rev. 1.3

164

Rev. 1.3 165

165

16.4. USB Clock Configuration

166

16.5. FIFO Management

167

16.5.2. FIFO Double Buffering

168

16.5.1. FIFO Access

168

16.6. Function Addressing

169

170 Rev. 1.3

170

Rev. 1.3 171

171

16.8. Interrupts

172

Rev. 1.3 173

173

174 Rev. 1.3

174

Rev. 1.3 175

175

16.10. Endpoint0

176

Rev. 1.3 177

177

178 Rev. 1.3

178

Rev. 1.3 179

179

Section 16.5.1

180

Rev. 1.3 181

181

182 Rev. 1.3

182

Rev. 1.3 183

183

184 Rev. 1.3

184

Rev. 1.3 185

185

FIFO manually

185

186 Rev. 1.3

186

Rev. 1.3 187

187

17. SMBus

188

17.1. Supporting Documents

189

17.2. SMBus Configuration

189

17.3. SMBus Operation

189

17.3.1. Arbitration

190

17.4. Using the SMBus

191

192 Rev. 1.3

192

ClockSourceOverflow

192

Rev. 1.3 193

193

194 Rev. 1.3

194

Rev. 1.3 195

195

196 Rev. 1.3

196

Rev. 1.3 197

197

17.5. SMBus Transfer Modes

198

Rev. 1.3 199

199

17.5.2. Master Receiver Mode

200

17.5.3. Slave Receiver Mode

201

17.6. SMBus Status Decoding

202

Rev. 1.3 203

203

204 Rev. 1.3

204

18. UART0

205

RX Timer

206

Timer 1 UART

206

18.2.1. 8-Bit UART

207

18.2.2. 9-Bit UART

208

Rev. 1.3 209

209

210 Rev. 1.3

210

Rev. 1.3 211

211

212 Rev. 1.3

212

Rev. 1.3 213

213

214 Rev. 1.3

214

19.2. Data Format

215

Figure 19.4. UART1 Timi

215

19.3.1. Data Transmission

216

19.3.2. Data Reception

216

Rev. 1.3 217

217

218 Rev. 1.3

218

Rev. 1.3 219

219

220 Rev. 1.3

220

Rev. 1.3 221

221

222 Rev. 1.3

222

20.1. Signal Descriptions

223

224 Rev. 1.3

224

Rev. 1.3 225

225

20.4. SPI0 Interrupt Sources

226

20.5. Serial Clock Timing

227

228 Rev. 1.3

228

Rev. 1.3 229

229

230 Rev. 1.3

230

Rev. 1.3 231

231

232 Rev. 1.3

232

Rev. 1.3 233

233

234 Rev. 1.3

234

21. Timers

235

Section

236

Descriptions” on page 90

236

TR0 GATE0 INT0 Counter/Timer

236

Rev. 1.3 237

237

238 Rev. 1.3

238

Rev. 1.3 239

239

T1M1 T1M0 Mode

240

T0M1 T0M0 Mode

240

SCA1 SCA0 Prescaled Clock

241

242 Rev. 1.3

242

21.2. Timer 2

243

244 Rev. 1.3

244

To SMBus

245

Overflow

245

246 Rev. 1.3

246

Rev. 1.3 247

247

248 Rev. 1.3

248

21.3. Timer 3

249

250 Rev. 1.3

250

Rev. 1.3 251

251

252 Rev. 1.3

252

Rev. 1.3 253

253

254 Rev. 1.3

254

Crossbar

255

Port I/O

255

22.1. PCA Counter/Timer

256

22.2. Capture/Compare Modules

257

258 Rev. 1.3

258

Rev. 1.3 259

259

260 Rev. 1.3

260

22.2.4. Frequency Output Mode

261

262 Rev. 1.3

262

Rev. 1.3 263

263

22.3. Watchdog Timer Mode

264

22.3.2. Watchdog Timer Usage

265

266 Rev. 1.3

266

CPS2 CPS1 CPS0 Timebase

267

268 Rev. 1.3

268

Rev. 1.3 269

269

270 Rev. 1.3

270

23. C2 Interface

271

Code Command

272

23.2. C2 Pin Sharing

273

DOCUMENT CHANGE LIST

274

Rev. 1.3 275

275

CONTACT INFORMATION

276

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